1. Field of the Invention
Embodiments of the present invention relate generally to a method of tungsten layer formation.
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit densities. The demand for greater circuit densities necessitates a reduction in the dimensions of the integrated circuit components.
As the dimensions of the integrated circuit components are reduced (e.g., sub-micron dimensions), the materials used to fabricate such components contribute to the electrical performance thereof. For example, low resistivity metal interconnects (e.g., aluminum (Al) and copper (Cu)) provide conductive paths between the components on integrated circuits.
Referring to FIG. 1, the metal interconnects 2 are typically electrically isolated from each other by a bulk insulating material 4. When the distance between adjacent metal interconnects 2 and/or the thickness of the bulk insulating material 4 has sub-micron dimensions, capacitive coupling potentially occurs between such interconnects 2. Capacitive coupling between adjacent metal interconnects 2 may cause cross-talk and/or resistance-capacitance (RC) delay, which degrades the overall performance of the integrated circuit.
In order to minimize capacitive coupling between adjacent metal interconnects, low dielectric constant bulk insulating materials 4 (e.g., dielectric constants less than about 3.5) are used. Examples of low dielectric constant bulk insulating materials include silicon dioxide (SiO2), silicate glass and organosilicates, among others.
In addition, a barrier layer 6 is typically formed over the metal interconnects 2 as well as the bulk insulating material 4. The barrier layer 6 minimizes the diffusion of the metal from the metal interconnects 2 into a subsequently deposited insulating material layer 8. Diffusion of the metal from the metal interconnects 2 into the subsequently deposited insulating material layer 8 is undesirable because such diffusion can affect the electrical performance of the integrated circuit (e.g., cross-talk and or RC delay) or render it inoperable.
Silicon carbide is often used for the barrier layer 6. However, silicon carbide has a dielectric constant of about 4.0 to about 5.0. The dielectric constant of the silicon carbide in conjunction with the dielectric constant of the bulk insulating materials tends to increase the overall dielectric constant of the metal interconnect structure which may degrade the performance of the integrated circuit.
Thus, a need exists for a method to selectively deposit a barrier layer on a metal film.
A method to selectively deposit a barrier layer on a metal film formed on a substrate is described. The barrier layer may comprise a refractory metal such as, for example, tungsten (W). The barrier layer is selectively deposited on the metal film using a cyclical deposition process including a predetermined number of deposition cycles followed by a purge step.
In the cyclical deposition process, each deposition cycle comprises alternately adsorbing a refractory metal-containing precursor and a reducing gas on the metal film formed on the substrate in a process chamber. The refractory metal-containing precursor and the reducing gas react to form the barrier layer on the metal film. After a predetermined number of deposition cycles are completed, the process chamber is purged of both the refractory metal-containing precursor and the reducing gas. This deposition sequence of performing a predetermined number of deposition cycles followed by a process chamber purge may be repeated until a desired barrier layer thickness is achieved.
The predetermined number of deposition cycles is selected to take advantage of differences in the number of deposition cycles needed to start depositing the barrier material on different types of material layers. Thus, the predetermined number of deposition cycles is advantageously selected to start deposition of the barrier material on the metal film but be less than the number of deposition cycles needed to start deposition of such barrier material on layers surrounding the metal film. As such, barrier material is only deposited on the metal film without being deposited on any surrounding material layers.
The selective deposition of the barrier layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the barrier layer is used as a cap layer for a metal feature in a damascene structure. For such an embodiment, a preferred process sequence includes providing a substrate having metal features formed thereon that are surrounded by a dielectric oxide. A barrier layer is selectively deposited on the metal features using a cyclical deposition process in which a predetermined number of deposition cycles, each comprising alternately adsorbing a refractory metal-containing precursor and a reducing gas on the metal features, is followed by a process chamber purge step. The cyclical deposition process is repeated until a desired thickness for the barrier layer is achieved. After the barrier layer is selectively deposited on the metal features, one or more insulating layers are formed thereon and patterned to define vias therethrough to the barrier layer formed on the metal features. Thereafter, the damascene structure is completed by filling the vias with a conductive material.